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Comparison A-Data Lancer RGB DDR5 2x16Gb AX5U5600C3616G-DCLARBK vs Kingston Fury Beast DDR5 RGB 2x16Gb KF556C36BBEAK2-32

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A-Data Lancer RGB DDR5 2x16Gb AX5U5600C3616G-DCLARBK
Kingston Fury Beast DDR5 RGB 2x16Gb KF556C36BBEAK2-32
A-Data Lancer RGB DDR5 2x16Gb AX5U5600C3616G-DCLARBKKingston Fury Beast DDR5 RGB 2x16Gb KF556C36BBEAK2-32
from £103.49 
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Memory capacity32 GB32 GB
Memory modules22
Form factorDIMMDIMM
TypeDDR5DDR5
Memory ranksingle rank
Specs
Memory speed5600 MHz5600 MHz
Clock speed44800 MB/s44800 MB/s
CAS latencyCL36CL36
Memory timing36-36-3636-38-38
Voltage1.25 V1.25 V
Coolingradiatorradiator
Module profilestandardstandard
Module height40 mm42.23 mm
More features
overclocking series
XMP
EXPO support
overclocking series
XMP
EXPO support
Lightingmulti compatibilitymulti compatibility
Color
Added to E-Catalogmarch 2023october 2022

Memory rank

The number of ranks provided in the memory bar.

The rank in this case is called one logical module — a chipset with a total capacity of 64 bits. If there is more than one rank, this means that several logical ones are implemented on one physical module, and they use the data transmission channel alternately. A similar design is used in order to achieve large amounts of RAM with a limited number of slots for individual brackets. At the same time, it should be said that for consumer computers, you can not pay much attention to the memory rank — more precisely, peer-to-peer modules are quite enough for them. But for servers and powerful workstations, two-, four- and even eight-rank solutions are produced.

Note that other things being equal, a larger number of ranks allows achieving larger volumes, however, it requires more computing power and increases the load on the system.

Memory timing

Timing is a term that refers to the time it takes to complete an operation. To understand the timing scheme, you need to know that structurally RAM consists of banks (from 2 to 8 per module), each of which, in turn, has rows and columns, like a table; when accessing memory, the bank is selected first, then the row, then the column. The timing scheme shows the time during which the four main operations are performed when working with RAM, and is usually written in four digits in the format CL-Trcd-Trp-Tras, where

CL is the minimum delay between receiving a command to read data and the start of their transfer;

Trcd — the minimum time between the selection of a row and the selection of a column in it;

Trp is the minimum time to close a row, that is, the delay between the signal and the actual closing. Only one bank line can be opened at a time; Before opening the next line, you must close the previous one.

Tras — the minimum time the row is active, in other words, the shortest time after which the row can be commanded to close after it has been opened.

Time in the timing scheme is measured in cycles, so the actual memory performance depends not only on the timing scheme, but also on the clock frequency. For example, 1600 MHz 8-8-8-24 memory will run at the same speed as 800 MHz 4-4-4-12 memory—in either case timings, if expressed in nanoseconds, will be 5-5-5-15.
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