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Jehiatek ICESugar FPGA Development Board Open Source RISC-V Based on ICE40UP5k USB-C Interface for IoT/Edge AI Projects

Photos - Printer Part Jehiatek ICESugar FPGA Development Board Open Source RISC-V Based on ICE40UP5k USB-C Interface for IoT/Edge AI Projects
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Features iCE40UP5k main chip, 5280 LUT/128KB SPRAM/PLL/ SPI///PWM On-board iCELink debugger, supporting drag-and-drop programming, USB CDC serial...
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