Memory rank
The number of ranks provided in the memory bar.
The rank in this case is called one logical module — a chipset with a total capacity of 64 bits. If there is more than one rank, this means that several logical ones are implemented on one physical module, and they use the data transmission channel alternately. A similar design is used in order to achieve large amounts of RAM with a limited number of slots for individual brackets. At the same time, it should be said that for consumer computers, you can not pay much attention to the memory rank — more precisely, peer-to-peer modules are quite enough for them. But for servers and powerful workstations, two-, four- and even eight-rank solutions are produced.
Note that other things being equal, a larger number of ranks allows achieving larger volumes, however, it requires more computing power and increases the load on the system.
CAS latency
This term refers to the time (more precisely, the number of memory cycles) that passes from the processor's request to read data to granting access to the first of the cells containing the selected data. CAS latency is one of the timings (for more details, see the "Memory Timings Scheme" section, where this parameter is designated as CL) — which means that it affects performance: the lower the CAS, the faster this memory module works. However this is true only for the same clock frequency (for more details, see ibid.).
Now there are memory modules on the market with the following CAS latency values:
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
24,
30,
32,
36,
38,
40,
42,
46.
Memory timing
Timing is a term that refers to the time it takes to complete an operation. To understand the timing scheme, you need to know that structurally RAM consists of banks (from 2 to 8 per module), each of which, in turn, has rows and columns, like a table; when accessing memory, the bank is selected first, then the row, then the column. The timing scheme shows the time during which the four main operations are performed when working with RAM, and is usually written in four digits in the format CL-Trcd-Trp-Tras, where
CL is the minimum delay between receiving a command to read data and the start of their transfer;
Trcd — the minimum time between the selection of a row and the selection of a column in it;
Trp is the minimum time to close a row, that is, the delay between the signal and the actual closing. Only one bank line can be opened at a time; Before opening the next line, you must close the previous one.
Tras — the minimum time the row is active, in other words, the shortest time after which the row can be commanded to close after it has been opened.
Time in the timing scheme is measured in cycles, so the actual memory performance depends not only on the timing scheme, but also on the clock frequency. For example, 1600 MHz 8-8-8-24 memory will run at the same speed as 800 MHz 4-4-4-12 memory—in either case timings, if expressed in nanoseconds, will be 5-5-5-15.
Lighting sync
The timing technology provided by the backlit memory module (see "Options").
Synchronization itself allows you to "match" the backlighting of the memory with the backlighting of other system components — the motherboard, processor, graphics card, case, keyboard, mouse, etc. Thanks to this matching, all components can change colour synchronously, turn on / off at the same time, etc. The specific features of the operation of such a backlight depend on the synchronization technology used, and, usually, each manufacturer has its own (Aura Sync for Asus, RGB Fusion for Gigabyte, etc.). The compatibility of the components also depends on this: they must all support the same technology. So the easiest way to achieve backlight compatibility is to collect components from the same manufacturer. However, there are many memory modules in the multi compatibility format — that is, capable of working with several backlight technologies at once. Usually, such memory is produced by manufacturers that do not have their own backlight technologies; a specific list of compatible technologies should be specified separately.
